1. TECHNICAL FIELD
This invention generally relates to semiconductor devices, and more specifically relates to methods and structures to reduce latch-up.
2. BACKGROUND ART
As integrated semiconductor devices continue to grow in complexity, there is a constant need to increase the density of the semiconductor devices. This increase in density creates several problems that can cause devices failures if not addressed. One such problem is the propensity for semiconductor devices, particularly CMOS devices, to "latch-up." Latch-up is a well known problem caused by unwanted transistor action between elements of the integrated circuit. This unwanted transistor action can be triggered by a wide variety of events, and can cause the semiconductor device to fail.
Latch-up is generally caused by the close proximity of n-channel and p-channel devices in modem CMOS devices. For example, a typical CMOS device fabricated on a p-type substrate would contain a p-channel device fabricated in a n-well and an n-channel device fabricated in a p-well, with only a short distance between the wells. This structure inherently forms a parasitic lateral bipolar structure (NPN) and parasitic vertical bipolar structure (PNP). Under certain biasing conditions the PNP structure can supply base current to the NPN structure (or vice versa), causing a large current to flow from the PNPN anode to cathode. When a PNPN devices triggers, the PNPN undergoes a transition from a low current.backslash.high voltage state to a low voltage/high current state. In some cases, the low voltage/high current state can lead to thermal runaway and destruction of the elements involved in the formation of the PNPN parasitic element.
For example, turning to FIG. 30, a CMOS device portion 800 is shown. The exemplary CMOS portion 800 is formed in p+ substrate 802 having a p-epitaxial layer 804. The CMOS portion 800 includes an n-channel device (of which only the first N++ diffusion 806 is shown) formed in a P-well 808 and a p-channel device (of which only the first P++ diffusion 810 is shown) formed in an N-well 812. The two devices are separated by a shallow trench isolation (STI) 814.
One parasitic lateral bipolar structure (NPN) is formed by the N++ diffusion 806, the P-well 808/P epitaxial layer 804, and the N-well 812 respectively. When latch-up occurs, the structure acts as a lateral bipolar NPN transistor with the N++ diffusion 806 acting as its emitter, P-well 808 and P epitaxial layer 804 acting as its base, and N-well 812 acting as the collector. N++ diffusion 806 injects electrons into P-well 808. The injected electrons are collected by N-well 812.
Likewise a parasitic vertical bipolar structure (PNP) is formed by the P++ diffusion 810, the N-well 812 and the P epitaxial layer 804, with the P++ diffusion 810 acting as its emitter, N-well 812 acting as its base, and P epitaxial layer 804 acting as its collector. Holes injected from P++ diffusion 810 into N-well 812 are collected by P epitaxial layer 804. The flow of holes from N-well 812 to P epitaxial layer 804 produces a corresponding flow of electrons from P epitaxial layer 804 to N-well 812, thereby enhancing the transfer effect of the NPN lateral bipolar structure.
This positive feedback action can cause the NPNP structure to latch-up. Of course, this is just one example of latch-up and where it can occur on a CMOS device, and latch-up can occur at other NPNP or PNPN paths throughout a typical CMOS device.
The propensity for CMOS devices to latch-up has been addressed in several ways. One way involves reducing the "gain" of the transistor type action. The gain is a function of the minority carrier lifetime in the base region. Reducing the gain reduces the propensity of the CMOS device to latch-up by increasing the voltage (known as the "trigger voltage") that must be applied to have the parasitic PNPN undergo a negative resistance state, which can lead to CMOS latch-up.
The gain of a parasitic transistor in a CMOS device is a function of many parameters, such as well profile design and P+/N+ spacings. In particular, the lateral and vertical profile can influence the parasitic bipolar gain of the lateral and vertical parasitic transistors respectively. Thus, the placement and control of the well-profile edge can strongly influence the latch-up characteristics of an advanced CMOS process. Today, the P-well-to-N-well spacing control is determined in part by overlay variations. As the devices are scaled and the P+ to N+ space decreases, the ability to limit the parasitic gain by controlling the well profile using prior art fabrication technologies will be increasing problematic.
Another method in dealing with latch-up is to raise the latch-up holding voltage. The latch-up holding voltage is the lowest stable voltage that can support a large current after latch-up is triggered. By increasing the latch-up holding voltage, the latch-up immunity is increased and the likelihood of the circuit being damaged is decreased. The optimal situation is to have a holding voltage greater than the burn-in voltage, typically 1.5 volts above the nominal supply voltage (Vdd).
Shallow trench isolation (STI) has been used between the n-channel and p-channel devices to minimize the likelihood of latch-up. However, when CMOS technologies are scaled to smaller dimensions, all geometric parameters including the STI dimensions are reduced. As the STI depth and/or width is reduced, latch-up immunity is decreased as a result of a higher transistor current gain and lower latch-up holding voltages. If the latch-up holding voltage is reduced too much, i.e., to less than the burn-in voltage, immunity to latch-up is compromised.
The prior art methods are thus unable to provide sufficient latch-up immunity in CMOS devices as the size of the devices, particular the isolation regions between the devices is decreased. Thus, there is a need for improved methods for increasing the latch-up immunity of CMOS devices that will allow for further device scaling and increased device density.